This invention relates to a walled-emitter bipolar transistor, and to a method of fabricating such a transistor.
Walled-emitter transistors, that is to say transistors in which sidewall contact between the base and the emitter is eliminated, offer the advantages of lower capacitance and greater speed than comparable `conventional` transistors. As with other transistors, there is a strong incentive to reduce the size of such devices in order to further increase their operating speed. The consequent reductions in feature size make the use of a self-aligned fabrication process increasingly necessary, but heretofore there have been no simple self-aligned fabrication processes for the manufacture of walled-emitter transistors.